1. Field of the Invention
The present invention relates to a method of making a multi-layer structure for making a metal-insulator-metal capacitor (MMC), and particularly to a method of making a multi-layer structure for making a double metal-insulator-metal capacitor (double MMC) structure having high capacitance density.
2. Description of the Prior Art
Various capacitor structures are used as electronic elements in integrated circuits such as radio frequency integrated circuits (RFIC), and monolithic microwave integrated circuits (MMIC).
Such capacitor structures include, for example, metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors and metal-insulator-metal (MIM) capacitors. For some applications, MIM capacitors can provide certain advantages over MOS and p-n junction capacitors because the frequency characteristics of MOS and p-n junction capacitors may be restricted as a result of depletion layers that form in the semiconductor electrodes. An MIM capacitor can exhibit improved frequency and temperature characteristics. Furthermore, MIM capacitors can be formed in the metal interconnect layers, thereby reducing CMOS transistor process integration interactions or complications.
Structurally, an MIM capacitor typically includes an insulating layer, such as a PECVD dielectric, disposed between lower and upper electrodes. To increase the circuit density and reduce the cost, large capacitance density is highly desirable. U.S. Pat. No. 6,977,198, issued Dec. 20, 2005 to Gau, assigned to United Microelectronics Corp., discloses a metal-insulator-metal (MIM) capacitor and a fabrication method for making it. The MIM capacitor has doubled capacitance per unit capacitor. Such MIM capacitor is also referred to as double MMC. As shown in FIG. 1, a MIM capacitor 10 comprises a first metal plate 12, a second metal plate 14 stacked above the first metal plate 12. The second metal plate 14 is electrically isolated from the first metal plate 12 by a first capacitor dielectric layer 13. A third metal plate 16 is stacked above the second metal plate 14 and is electrically isolated from the second metal plate 14 by a second capacitor dielectric layer 15. A cap layer 22 is deposited on the third metal plate 16. The cap layer 22 may be made of silicon oxide or silicon nitride. The MIM capacitor 10 is defined on a substrate 100 and covered with an inter-metal dielectric (IMD) layer 120. The first metal plate 12, the first capacitor dielectric layer 13, and the second metal plate 14 constitute a first capacitor (C1) or lower capacitor. The second metal plate 14, the second capacitor dielectric layer 15, and the third metal plate 16 constitute a second capacitor (C2) or upper capacitor. The first metal plate 12 of the MIM capacitor 10 is electrically connected to a first conductive terminal 42 through at least one conductive via 31 that penetrates through the IMD layer 120. The second metal plate 14 is electrically connected to a second conductive terminal 44 through at least one conductive via 32. The third metal plate 16 is electrically connected to the first conductive terminal 42 through at least one conductive via 33 that penetrates through the IMD layer 120 and the cap layer 22. This invention features a sandwich-like MIM capacitor structure consists of the lower capacitor C1 and the upper capacitor C2. The first metal plate 12, namely, one electrode of the lower capacitor C1, is electrically coupled with the third metal plate 16, namely, one electrode of the upper capacitor C2. The second metal plate 14 serves as a common electrode of the lower capacitor C1 and the upper capacitor C2 and is interposed between the first metal plate 12 and the third metal plate 16.
There is still a need for improvement of a double MMC structure to achieve higher breakdown voltage of double MMC (BVD) and longer time dependent dielectric breakdown (TDDB) lifetime.